The present invention relates to a signal process of a reproducing unit in a communication system or a recording/reproducing apparatus and, more particularly, to a technique of Viterbi decoding used to decode a reproduction signal in a maximum likelihood manner.
A Viterbi decoder is used to, for example, detect and correct an error in a signal subjected to waveform equalization at the time of reproducing a signal in a communication system or a recording/reproducing apparatus. By using waveform equalization and Viterbi decoding in a signal process, BER (Bit Error Rate) can be decreased.
FIG. 9 is a diagram showing the internal configuration of a path storing circuit provided in a conventional Viterbi decoder. Shown in FIG. 9 are path selection signals SEL0 and SEL1, an initial value 21 of a path holding part, path holding parts 31, 32, . . . , and 3n for holding a survivor path, and selectors 4 for selecting a value to be input to the path holding parts 31 to 3n in accordance with the path selection signals SEL0 and SEL1. The path holding parts 31 to 3n are provided at a plurality of stages (“n” stages) and each stage corresponds to time.
FIGS. 10 and 11 are a state transition diagram and a trellis diagram, respectively, showing states in Viterbi decoding. FIGS. 10 and 11 show six states of S0, S1, S2, S3, S4, and S5. Each of the states S0 and S5 has a branch pattern. As a modulating system, an 8–16 modulation code is used. The 8–16 modulation has a characteristic that the length of continuous sequences of the same code of a signal modulated lies in a range from 2 to 10. After NRZI transform, the characteristic becomes that the length of continuous sequences of the same code of the signal lies in a range from 3 to 11.
Each of the path holding parts 31, 32, . . . , and 3n has delay circuits of the number corresponding to the number of states. The top delay circuit and the bottom delay circuit receive signals selected according to the path selection signals SEL0 and SEL1, respectively. With such a configuration, the path holding part 3n at the final stage has the oldest signal. When a signal is decoded by maximum likelihood decoding, output values of all of the delay circuits of the path holding part 3n at the final stage become the same value. In other words, when output values of the delay circuits of the path holding part 3n at the final stage are not the same value, it means that an error occurs in decoding.
When circuits are formed in an LSI, in many cases, an output value of one of the delay circuits of the path holding part 3n is used as an output value of a path storing circuit and a maximum likelihood decision circuit at the post stage is not provided in consideration of a circuit scale. In order to improve the performance of Viterbi decoding, consequently, the number of stages of the path holding parts is usually increased.
In order to improve the performance of Viterbi decoding, there is also a case that a majority decision circuit is provided. FIG. 12 is a diagram showing an example of the configuration of a path storing circuit including a conventional majority decision circuit. In the configuration of FIG. 12, a majority decision circuit 80 receives output values of all of delay circuits of the path holding part 3n at the final stage, makes a decision by a majority, and outputs the majority value as an output value of the path storing circuit. With the configuration, improvement in performance of Viterbi decoding is realized.
However, a problem occurs such that the circuit scale increases vainly in order to realize improvement in performance of Viterbi decoding.
Specifically, in the case of increasing the number of stages of the path holding parts to improve the performance of Viterbi decoding, the circuit scale of the path storing circuit accordingly increases. In the case of making a decision by a majority by using all of state values to improve the performance of Viterbi decoding, a large-scale majority decision circuit is required. The circuit scale of the path storing circuit increases by the increased amount of the majority decision circuit and it also disturbs high processing speed of the circuit.